(1) Field of the Invention
This invention concerns methods for manufacturing substrates with large or difficult to planarize features such as large step height features, large width features or features of varying pattern densities. Such difficult to polish features are found in substrates such as photonic light circuits (PLC's) and micro-electro-mechanical systems (MEM's) which are also known as microelectromechanisms. The methods of this invention employ reverse mask etching and chemical mechanical polishing (CMP) techniques to planarize the difficult to polish feature with little dishing and with little edge loss.
(2) Description of the Art
Manufacturing processes for integrated circuits are well known in the art. Integrated circuits are typically formed on a substrate by the sequential deposition of conductive, semiconductive or insulating layers onto a silicon wafer. After deposition, each layer can be etched to create circuitry features. Integrated circuit fabrication processes generally require a subsequent layer to be deposited upon a planar surface of a previous layer. Chemical mechanical planarization (CMP) is used to planarize an integrated circuit layer in order to prepare it for the deposition of a subsequent layer.
The procedures used to manufacture integrated circuits are only starting to be applied to the manufacture of other electronic devices such as photonic light circuits (PLC's) and microelectronic mechanism (MEM's). However, the size (width and depth) and densities of features applied to such substrates are very different that features applied to IC's. This makes it impossible to use chemical mechanical polishing to planarize certain substrate layers without introducing undesirable effects and features such as dishing. During CMP of MEM's and PLC's, localized differences in polish pressure cause small features to polish faster than wider gaps, and oxide layers applied to narrow features polish slower than oxide applied to larger features in the same deposition step. Due to the high feature precision requirements of substrates such as PLC's and MEM's, undesirable features caused by CMP are a major and unsolved problem.
FIGS. 1A-1D are cross-section views of embodiments of electronic devices that include features that are currently difficult to planarized by CMP. FIG. 1A is an electronic substrate cross-section that includes a large width feature 100 that is associated with a plurality of features 102 having very small widths. The substrate is covered by a deposited material 104 that fills large width feature 100 and small width features 102 and is to be planarized by CMP. The typical result of CMP of the substrate of FIG. 1A is shown in FIG. 1B. FIG. 1B depicts a substrate 100 including material 104 located above-large width feature 100 is dished to a greater extent thereby leaving the substrate with an unacceptable deviation from planarity. Dishing of the large density of small width features also occurs and usually results in dissimilar trench depths. The dishing occurs primarily because material 104 applied over large width feature 100 typically has a thickness H1 that is less than the thickness H2 of material 104 above the plurality of narrow features 102. Furthermore, polishing material 104 until it is planar with the surface of substrate 101 often causes the corners 105 associated of large width feature 100 to become rounded. Such rounded corners are undesirable for most electronic substrates including photonic light circuits which require features with sharp edges to minimize undesirable features in subsequently applied layers and to improve the efficiency of subsequent lithography steps.
Problems also occur when applying CMP techniques to add a large step height features to electronic substrates. FIG. 1C shows an electronic substrate including a large step height feature 110. Large step height feature 110 will typically have a height of from 2 to about 50 microns. In order to deposit a layer of material 111 into large step height feature 110, the step height H3 (the peak to valley height) of the top surface of material applied to the surface of the substrate and into large step height feature 110 can be quite large. Using CMP material 111 to planarize it with the surface 112 of substrate 109 is very difficult because using CMP to polish a thick layer of material causes dishing 113 and undesirably rounded corners 114 at the junction of the large step height feature 110 and substrate surface 112.
As integrated circuit manufacturing techniques are applied to larger and more diverse electronic substrates such as PLC's and MEM's, there remains a need for processes and techniques for planarizing the surfaces of such substrates without substantial deviation from planarity.